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sunflower2333sunflower2333
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add sm8450 table definitions (may contain wrong def)
1 parent 9a1a800 commit 2ef2545

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11 files changed

+4659
-13
lines changed

11 files changed

+4659
-13
lines changed

‎include/vendor/qcom/sm8450/csrt.h‎

Lines changed: 4321 additions & 0 deletions
Large diffs are not rendered by default.

‎include/vendor/qcom/sm8450/dbg2.h‎

Lines changed: 152 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,152 @@
1+
#pragma once
2+
#include "table_header.h"
3+
#include <common/dbg2.h>
4+
5+
// DEBUG UART
6+
#define UARD_NAMESPACE_STRING "\\_SB.UARD"
7+
// USB
8+
#define URS0_NAMESPACE_STRING "\\_SB.URS0"
9+
10+
#define USB_OEM_DATA_SIZE 0x94
11+
12+
#define UARD_NUM_GAS 1
13+
#define URS0_NUM_GAS 2
14+
15+
/* typedef */
16+
DBG2_DEFINE_DEBUG_DEVICE_INFO_STRUCTURE(UARD, UARD_NUM_GAS,
17+
sizeof(UARD_NAMESPACE_STRING), 0);
18+
DBG2_DEFINE_DEBUG_DEVICE_INFO_STRUCTURE(URS0HS, URS0_NUM_GAS,
19+
sizeof(URS0_NAMESPACE_STRING),
20+
USB_OEM_DATA_SIZE);
21+
DBG2_DEFINE_DEBUG_DEVICE_INFO_STRUCTURE(URS0SS, URS0_NUM_GAS,
22+
sizeof(URS0_NAMESPACE_STRING),
23+
USB_OEM_DATA_SIZE);
24+
25+
DBG2_DEFINE_TABLE(DBG2_DEFINE_DEVICE_INFO_IN_TABLE(UARD);
26+
DBG2_DEFINE_DEVICE_INFO_IN_TABLE(URS0HS);
27+
DBG2_DEFINE_DEVICE_INFO_IN_TABLE(URS0SS););
28+
DBG2_DEFINE_WITH_MAGIC;
29+
30+
/* Initialize struct */
31+
DBG2_START{
32+
DBG2_DECLARE_HEADER,
33+
DBG2_DECLARE_HEADER_EXTRA_DATA(3), // Info count
34+
/* Debug UART */
35+
DBG2_DECLARE_QCOM_SDM845_UARD(UARD, UARD_NAMESPACE_STRING,
36+
UARD_BASE_ADDRESS),
37+
/* Primary Core USB HS (Synopsys)*/
38+
.URS0HS =
39+
{
40+
.Revision = 1,
41+
.Length = sizeof(DBG2_GET_DEBUG_DEVICE_INFO_STRUCTURE_NAME(URS0HS)),
42+
.NumOfGenericAddrRegs = URS0_NUM_GAS,
43+
.NamespaceString = URS0_NAMESPACE_STRING,
44+
.NamespaceStringLen = sizeof(URS0_NAMESPACE_STRING),
45+
.NamespaceStringOffset =
46+
offsetof(DBG2_GET_DEBUG_DEVICE_INFO_STRUCTURE_NAME(URS0HS),
47+
NamespaceString),
48+
.OemDataLen = USB_OEM_DATA_SIZE,
49+
.OemDataOffset = offsetof(
50+
DBG2_GET_DEBUG_DEVICE_INFO_STRUCTURE_NAME(URS0HS), OemData),
51+
.PortType = DBG2_DEBUG_PORT_TYPE_NETWORK,
52+
.PortSubtype = DBG2_DEBUG_PORT_SUBTYPE_USB_SYNOPSYS,
53+
.BaseAddrRegOffset =
54+
offsetof(DBG2_GET_DEBUG_DEVICE_INFO_STRUCTURE_NAME(URS0HS),
55+
BaseAddrRegister),
56+
.AddrSizeOffset = offsetof(
57+
DBG2_GET_DEBUG_DEVICE_INFO_STRUCTURE_NAME(URS0HS), AddressSize),
58+
.BaseAddrRegister =
59+
{
60+
{
61+
.AddressSpaceID = 00,
62+
.RegisterBitWidth = 0x20,
63+
.RegisterBitOffset = 0,
64+
.AccessSize = 0x20,
65+
.Address = 0xA600000,
66+
},
67+
{
68+
.AddressSpaceID = 00,
69+
.RegisterBitWidth = 0x20,
70+
.RegisterBitOffset = 0,
71+
.AccessSize = 0x20,
72+
.Address = 0xA600000,
73+
},
74+
},
75+
.AddressSize = {0xFFFFF, 0x1000},
76+
.OemData = {0x05, 0x00, 0x00, 0x00, 0x32, 0x58, 0x49, 0x46, 0x03,
77+
0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0xc7,
78+
0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00,
79+
0x00, 0x00, 0x02, 0x00, 0x00, 0x10, 0x88, 0x0f, 0x00,
80+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x10, 0x00,
81+
0x02, 0x00, 0x00, 0xb4, 0x88, 0x0f, 0x00, 0x00, 0x00,
82+
0x00, 0x00, 0xeb, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00,
83+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
84+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
85+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
86+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
87+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
88+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
89+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
90+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
91+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
92+
0x43, 0x42, 0x53, 0x55},
93+
},
94+
/* Primary Core USB SS (Synopsys)*/
95+
.URS0SS =
96+
{
97+
.Revision = 1,
98+
.Length = sizeof(DBG2_GET_DEBUG_DEVICE_INFO_STRUCTURE_NAME(URS0SS)),
99+
.NumOfGenericAddrRegs = URS0_NUM_GAS,
100+
.NamespaceString = URS0_NAMESPACE_STRING,
101+
.NamespaceStringLen = sizeof(URS0_NAMESPACE_STRING),
102+
.NamespaceStringOffset =
103+
offsetof(DBG2_GET_DEBUG_DEVICE_INFO_STRUCTURE_NAME(URS0SS),
104+
NamespaceString),
105+
.OemDataLen = USB_OEM_DATA_SIZE,
106+
.OemDataOffset = offsetof(
107+
DBG2_GET_DEBUG_DEVICE_INFO_STRUCTURE_NAME(URS0SS), OemData),
108+
.PortType = DBG2_DEBUG_PORT_TYPE_NETWORK,
109+
.PortSubtype = DBG2_DEBUG_PORT_SUBTYPE_USB_SYNOPSYS,
110+
.BaseAddrRegOffset =
111+
offsetof(DBG2_GET_DEBUG_DEVICE_INFO_STRUCTURE_NAME(URS0SS),
112+
BaseAddrRegister),
113+
.AddrSizeOffset = offsetof(
114+
DBG2_GET_DEBUG_DEVICE_INFO_STRUCTURE_NAME(URS0SS), AddressSize),
115+
.BaseAddrRegister =
116+
{
117+
{
118+
.AddressSpaceID = 00,
119+
.RegisterBitWidth = 0x20,
120+
.RegisterBitOffset = 0,
121+
.AccessSize = 0x20,
122+
.Address = 0xA600000,
123+
},
124+
{
125+
.AddressSpaceID = 00,
126+
.RegisterBitWidth = 0x20,
127+
.RegisterBitOffset = 0,
128+
.AccessSize = 0x20,
129+
.Address = 0xA600000,
130+
},
131+
},
132+
.AddressSize = {0xFFFFF, 0x1000},
133+
.OemData = {0x05, 0x00, 0x00, 0x00, 0x32, 0x58, 0x49, 0x46, 0x03,
134+
0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x04, 0xc7,
135+
0x00, 0x00, 0xff, 0xe1, 0xff, 0xff, 0x00, 0x00, 0x00,
136+
0x00, 0x00, 0x01, 0x00, 0x00, 0x10, 0x88, 0x0f, 0x00,
137+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x10, 0x00,
138+
0x02, 0x00, 0x00, 0xb4, 0x88, 0x0f, 0x00, 0x00, 0x00,
139+
0x00, 0x00, 0xeb, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00,
140+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
141+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
142+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
143+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
144+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
145+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
146+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
147+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
148+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
149+
0x43, 0x42, 0x53, 0x55},
150+
},
151+
152+
} DBG2_END

‎include/vendor/qcom/sm8450/facp.h‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
#pragma once
2+
#include "table_header.h"
3+
#include <common/facp.h>
4+
5+
#define FACP_RESET_REG_ADDRESS 0x9020B4ULL
6+
7+
FACP_DEFINE_TABLE;
8+
FACP_DEFINE_WITH_MAGIC;
9+
10+
FACP_START{
11+
FACP_DECLARE_HEADER,
12+
/*
13+
* All parts not assigned are 0 by default. Only assign used parts here.
14+
*/
15+
.FacpDataStructure =
16+
{
17+
.Preferred_PM_Profile = FACP_PM_PROFILE_TABLET,
18+
.Flags =
19+
FACP_FLAG_HW_REDUCED_ACPI | FACP_FLAG_LOW_POWER_S0_IDLE_CAPABLE,
20+
.ResetReg =
21+
{
22+
.AddressSpaceId =
23+
ACPI_GAS_ADDR_SPACE_ID_EMBEDDED_CONTROLLER, // Embeded controller
24+
.RegisterBitWidth = 0,
25+
.RegisterBitOffset = 0,
26+
.AccessSize = ACPI_GAS_ACCESS_SIZE_DWORD,
27+
.Address = FACP_RESET_REG_ADDRESS,
28+
},
29+
.ResetValue = 0x01,
30+
.ARM_BOOT_ARCH = FACP_ARM_BOOT_ARCH_PSCI_COMPLIANCE,
31+
.HypervisorVendorIdentity =
32+
ACPI_FACP_HYP_VENDOR_ID, // 'M', 'O', 'C', 'Q'
33+
},
34+
} FACP_END

‎include/vendor/qcom/sm8450/facs.h‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
#pragma once
2+
#include "table_header.h"
3+
#include <common/facs.h>
4+
5+
FACS_DEFINE_TABLE;
6+
FACS_DEFINE_WITH_MAGIC;
7+
8+
FACS_START{
9+
/* FACS does not have any header ~ */
10+
// Use default data here (all zero except signature, length, version)
11+
FACS_FILL_DEFAULT_DATA,
12+
} FACS_END

‎include/vendor/qcom/sm8450/gtdt.h‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
#pragma once
2+
#include "table_header.h"
3+
#include <common/gtdt.h>
4+
#include <stddef.h>
5+
6+
GTDT_DEFINE_TABLE();
7+
GTDT_DEFINE_WITH_MAGIC;
8+
9+
GTDT_START{
10+
GTDT_DECLARE_HEADER,
11+
.GTDTHeaderExtraData =
12+
{
13+
.CntControlBasePhyAddress = 0xFFFFFFFFFFFFFFFFULL,
14+
.SecureEL1TimerGSI = 0x1D,
15+
.SecureEL1TimerFlags = GTDT_BLOCK_S_NS_ELX_TIMER_FLAG_ALWATS_ON_CAP,
16+
.NSEL1TimerGSI = 0x1E,
17+
.NSEL1TimerFlags = GTDT_BLOCK_S_NS_ELX_TIMER_FLAG_ALWATS_ON_CAP,
18+
.VirtualEL1TimerGSI = 0x1B,
19+
.VirtualEL1TimerFlags = GTDT_BLOCK_S_NS_ELX_TIMER_FLAG_ALWATS_ON_CAP,
20+
.EL2TimerGSI = 0x1A,
21+
.EL2TimerFlags = GTDT_BLOCK_S_NS_ELX_TIMER_FLAG_ALWATS_ON_CAP,
22+
.CntReadBasePhyAddress = 0xFFFFFFFFFFFFFFFFULL,
23+
},
24+
} GTDT_END;

‎include/vendor/qcom/sm8450/iort.h‎

Whitespace-only changes.

‎include/vendor/qcom/sm8450/madt.h‎

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,44 @@
1+
#pragma once
2+
#include "table_header.h"
3+
#include <common/madt.h>
4+
5+
#define GICD_BASE_ADDRESS 0x17100000ULL
6+
#define GIC_ITS_BASE_ADDRESS 0x17140000ULL
7+
#define GICR_BASE_ADDRESS 0x17180000ULL
8+
#define GICR_STRIDE 0x40000ULL
9+
#define GICC_PERFORMANCE_INTERRUPT_GSI 0x17
10+
#define GICC_VGIC_MAINTENANCE_INTERRUPT 0x19
11+
#define GICC_MPIDR_CORE0 0x00000000ULL
12+
#define GICC_MPIDR_CORE1 0x00000100ULL
13+
#define GICC_MPIDR_CORE2 0x00000200ULL
14+
#define GICC_MPIDR_CORE3 0x00000300ULL
15+
#define GICC_MPIDR_CORE4 0x00000400ULL
16+
#define GICC_MPIDR_CORE5 0x00000500ULL
17+
#define GICC_MPIDR_CORE6 0x00000600ULL
18+
#define GICC_MPIDR_CORE7 0x00000700ULL
19+
#define GIC_VERSION GIC_V3
20+
#define NUM_ITS 1
21+
22+
MADT_DEFINE_TABLE(NUM_CORES, NUM_ITS, ACPI_MADT_TABLE_STRUCTURE_NAME);
23+
MADT_DEFINE_WITH_MAGIC;
24+
25+
MADT_START{
26+
/* Table Header */
27+
MADT_DECLARE_HEADER,
28+
MADT_DECLARE_HEADER_EXTRA_DATA(0, 0),
29+
/* GICD Structure */
30+
MADT_DECLARE_GICD_STRUCTURE(GICD_BASE_ADDRESS, GIC_VERSION),
31+
32+
/* GIC ITS Structure */
33+
MADT_DECLARE_GIC_ITS_STRUCTURE(0, GIC_ITS_BASE_ADDRESS, 0),
34+
35+
/* GICC Structure */
36+
MADT_DECLARE_GICC_STRUCTURE(0, 0, GICC_MPIDR_CORE0), // Core 0
37+
MADT_DECLARE_GICC_STRUCTURE(1, 1, GICC_MPIDR_CORE1), // Core 1
38+
MADT_DECLARE_GICC_STRUCTURE(2, 2, GICC_MPIDR_CORE2), // Core 2
39+
MADT_DECLARE_GICC_STRUCTURE(3, 3, GICC_MPIDR_CORE3), // Core 3
40+
MADT_DECLARE_GICC_STRUCTURE(4, 4, GICC_MPIDR_CORE4), // Core 4
41+
MADT_DECLARE_GICC_STRUCTURE(5, 5, GICC_MPIDR_CORE5), // Core 5
42+
MADT_DECLARE_GICC_STRUCTURE(6, 6, GICC_MPIDR_CORE6), // Core 6
43+
MADT_DECLARE_GICC_STRUCTURE(7, 7, GICC_MPIDR_CORE7), // Core 7
44+
} MADT_END;

‎include/vendor/qcom/sm8450/mcfg.h‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
#pragma once
2+
#include "table_header.h"
3+
#include <common/mcfg.h>
4+
5+
#define PCI_EC_SPACE_COUNT 2
6+
#define PCI_EC_0_BASE_ADDRESS 0x60000000ULL /* qcom,pcie@1c00000 */
7+
#define PCI_EC_1_BASE_ADDRESS 0x40000000ULL /* qcom,pcie@1c08000 */
8+
9+
10+
MCFG_DEFINE_TABLE(PCI_EC_SPACE_COUNT);
11+
MCFG_DEFINE_WITH_MAGIC;
12+
13+
14+
MCFG_START {
15+
MCFG_DECLARE_HEADER,
16+
MCFG_DECLARE_HEADER_EXTRA_DATA,
17+
MCFG_DECLARE_EC_SPACE_STRUCTURE(0, 0, PCI_EC_0_BASE_ADDRESS, 0x00, 0xFF), // PCI Segment 0
18+
MCFG_DECLARE_EC_SPACE_STRUCTURE(1, 1, PCI_EC_1_BASE_ADDRESS, 0x00, 0xFF), // PCI Segment 1
19+
} MCFG_END

‎include/vendor/qcom/sm8450/pptt.h‎

Lines changed: 4 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -4,14 +4,6 @@
44
#include <stddef.h>
55
#include <sys/cdefs.h>
66

7-
/* Platform specific configuration */
8-
#define NUM_CORES 8
9-
#define NUM_CLUSTERS 4
10-
#define NUM_SYSTEM 1
11-
#define L1_CACHES_COUNT 2 + 2
12-
#define L2_CACHES_COUNT 1
13-
#define L3_CACHES_COUNT 1
14-
157
#define SYSTEM_PRIVATE_RESOURCES_COUNT 2 // ID, L3 Cache
168
#define CLUSTER_PRIVATE_RESOURCES_COUNT 1 // L2 Cache
179
#define PHYSICAL_CPU_PRIVATE_RESOURCES_COUNT 2 // L1I, L1D
@@ -41,7 +33,7 @@ PPTT_START{
4133
// L1 Caches
4234
PPTT_DECLARE_SIMPLE_CACHE(2, PPTT_REFERENCE_CACHE(1)), // L1I
4335
PPTT_DECLARE_SIMPLE_CACHE(3, PPTT_REFERENCE_CACHE(1)), // L1D
44-
36+
4537
// L1 Caches (L2 shared)
4638
PPTT_DECLARE_SIMPLE_CACHE(4, 0), // L1I
4739
PPTT_DECLARE_SIMPLE_CACHE(5, 0), // L1D
@@ -55,23 +47,22 @@ PPTT_START{
5547
// Cluster 0 (2 cores)
5648
// - parents: System
5749
// - private resources: none
58-
PPTT_DECLARE_PROCESSOR_HIERARCHY_CLUSTER(0, 0, PPTT_REFERENCE_SYSTEM,
50+
PPTT_DECLARE_PROCESSOR_HIERARCHY_CLUSTER(0, 0, PPTT_REFERENCE_SYSTEM,
5951
PPTT_REFERENCE_CACHE(1)),
6052
// Cluster 1 (2 cores)
6153
// - parents: System
6254
// - private resources: none
63-
PPTT_DECLARE_PROCESSOR_HIERARCHY_CLUSTER(1, 0, PPTT_REFERENCE_SYSTEM,
55+
PPTT_DECLARE_PROCESSOR_HIERARCHY_CLUSTER(1, 0, PPTT_REFERENCE_SYSTEM,
6456
PPTT_REFERENCE_CACHE(1)),
6557
// Cluster 2 (3 cores)
6658
// - parents: System
6759
// - private resources: none
68-
PPTT_DECLARE_PROCESSOR_HIERARCHY_CLUSTER(2, 0, PPTT_REFERENCE_SYSTEM),
60+
PPTT_DECLARE_PROCESSOR_HIERARCHY_CLUSTER(2, 0, PPTT_REFERENCE_SYSTEM),
6961
// Cluster 3 (1 core)
7062
// - parents: System
7163
// - private resources: none
7264
PPTT_DECLARE_PROCESSOR_HIERARCHY_CLUSTER(3, 0, PPTT_REFERENCE_SYSTEM),
7365

74-
7566
// Physical CPUs
7667
// Cluster 0 CPUs (2 cores)
7768
// - parents: Cluster 0

‎include/vendor/qcom/sm8450/spcr.h‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
#pragma once
2+
#include "table_header.h"
3+
#include <common/spcr.h>
4+
5+
/* typedef */
6+
SPCR_DEFINE_TABLE;
7+
SPCR_DEFINE_WITH_MAGIC;
8+
9+
/* Initialize struct */
10+
SPCR_START{
11+
SPCR_DECLARE_HEADER,
12+
.SPCRHeaderExtraData =
13+
{
14+
.InterfaceType =
15+
DBG2_DEBUG_PORT_SUBTYPE_SERIAL_SDM845_7P372_MHZ_CLK,
16+
.BaseAddress =
17+
{
18+
.AddressSpaceID = 0x00, // System Memory Mapped
19+
.RegisterBitWidth = 0x20,
20+
.RegisterBitOffset = 0x00,
21+
.AccessSize = 0x20,
22+
.Address = UARD_BASE_ADDRESS,
23+
},
24+
.InterruptType = SPCR_INTERRUPT_TYPE_ARMH_GIC,
25+
.GlobalSystemInterrupt = UARD_GIC_SPI_INTERRUPT_NUMBER,
26+
.ConfiguredBaudRate = SPCR_CONFIGURED_BAUD_RATE_115200,
27+
.Parity = SPCR_PARITY_NO_PARITY,
28+
.StopBits = SPCR_STOP_BITS_ONE_STOP_BIT,
29+
.FlowControl = SPCR_FLOW_CONTROL_NONE,
30+
.TerminalType = SPCR_TERMINAL_TYPE_VT_ANSI,
31+
.PciDeviceId = 0xFFFF,
32+
.PciVendorId = 0xFFFF,
33+
},
34+
} SPCR_END;

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