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alaindargelasalaindargelas
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Merge pull request #4038 from alainmarcel/alainmarcel-patch-1
High conn binding fix
2 parents 1a6281d + fd4914d commit d4a5b19

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33 files changed

+111
-119
lines changed

33 files changed

+111
-119
lines changed

‎tests/AssertDelayError/AssertDelayError.log‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2628,7 +2628,7 @@ design: (work@tb_left_rotation)
26282628
|vpiName:clk
26292629
|vpiFullName:work@tb_left_rotation.clk
26302630
|vpiActual:
2631-
\_logic_net: (work@tb_left_rotation.left_rotation_inst.clk), line:2:16, endln:2:19
2631+
\_logic_net: (work@tb_left_rotation.clk), line:3:9, endln:3:12
26322632
|vpiLowConn:
26332633
\_ref_obj: (work@tb_left_rotation.left_rotation_inst.clk), line:9:10, endln:9:13
26342634
|vpiParent:
@@ -2659,7 +2659,7 @@ design: (work@tb_left_rotation)
26592659
|vpiName:reset
26602660
|vpiFullName:work@tb_left_rotation.reset
26612661
|vpiActual:
2662-
\_logic_net: (work@tb_left_rotation.left_rotation_inst.reset), line:3:16, endln:3:21
2662+
\_logic_net: (work@tb_left_rotation.reset), line:3:14, endln:3:19
26632663
|vpiLowConn:
26642664
\_ref_obj: (work@tb_left_rotation.left_rotation_inst.reset), line:10:10, endln:10:15
26652665
|vpiParent:
@@ -2690,7 +2690,7 @@ design: (work@tb_left_rotation)
26902690
|vpiName:in_data
26912691
|vpiFullName:work@tb_left_rotation.in_data
26922692
|vpiActual:
2693-
\_logic_net: (work@tb_left_rotation.left_rotation_inst.in_data), line:4:22, endln:4:29
2693+
\_logic_net: (work@tb_left_rotation.in_data), line:4:15, endln:4:22
26942694
|vpiLowConn:
26952695
\_ref_obj: (work@tb_left_rotation.left_rotation_inst.in_data), line:11:10, endln:11:17
26962696
|vpiParent:
@@ -2721,7 +2721,7 @@ design: (work@tb_left_rotation)
27212721
|vpiName:out_data
27222722
|vpiFullName:work@tb_left_rotation.out_data
27232723
|vpiActual:
2724-
\_logic_net: (work@tb_left_rotation.left_rotation_inst.out_data), line:5:22, endln:5:30
2724+
\_logic_net: (work@tb_left_rotation.out_data), line:5:16, endln:5:24
27252725
|vpiLowConn:
27262726
\_ref_obj: (work@tb_left_rotation.left_rotation_inst.out_data), line:12:10, endln:12:18
27272727
|vpiParent:
@@ -3277,7 +3277,7 @@ design: (work@tb_left_rotation)
32773277
|vpiName:clk
32783278
|vpiFullName:work@tb_left_rotation.clk
32793279
|vpiActual:
3280-
\_logic_net: (work@tb_left_rotation.left_rotation_inst.u_left_rotate_assertions.clk), line:2:11, endln:2:14
3280+
\_logic_net: (work@tb_left_rotation.left_rotation_inst.clk), line:2:16, endln:2:19
32813281
|vpiLowConn:
32823282
\_ref_obj: (work@tb_left_rotation.u_left_rotate_assertions.clk), line:38:6, endln:38:9
32833283
|vpiParent:

‎tests/AssertTempError/AssertTempError.log‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -4505,7 +4505,7 @@ design: (work@tb_UART)
45054505
|vpiName:clk
45064506
|vpiFullName:work@tb_UART.clk
45074507
|vpiActual:
4508-
\_logic_net: (work@tb_UART.uart_inst.clk), line:3:11, endln:3:14
4508+
\_logic_net: (work@tb_UART.clk), line:4:9, endln:4:12
45094509
|vpiLowConn:
45104510
\_ref_obj: (work@tb_UART.uart_inst.clk), line:11:10, endln:11:13
45114511
|vpiParent:
@@ -4536,7 +4536,7 @@ design: (work@tb_UART)
45364536
|vpiName:rst_n
45374537
|vpiFullName:work@tb_UART.rst_n
45384538
|vpiActual:
4539-
\_logic_net: (work@tb_UART.uart_inst.rst_n), line:4:11, endln:4:16
4539+
\_logic_net: (work@tb_UART.rst_n), line:4:14, endln:4:19
45404540
|vpiLowConn:
45414541
\_ref_obj: (work@tb_UART.uart_inst.rst_n), line:12:10, endln:12:15
45424542
|vpiParent:
@@ -4567,7 +4567,7 @@ design: (work@tb_UART)
45674567
|vpiName:rx
45684568
|vpiFullName:work@tb_UART.rx
45694569
|vpiActual:
4570-
\_logic_net: (work@tb_UART.uart_inst.rx), line:5:11, endln:5:13
4570+
\_logic_net: (work@tb_UART.rx), line:5:9, endln:5:11
45714571
|vpiLowConn:
45724572
\_ref_obj: (work@tb_UART.uart_inst.rx), line:13:10, endln:13:12
45734573
|vpiParent:
@@ -4598,7 +4598,7 @@ design: (work@tb_UART)
45984598
|vpiName:tx
45994599
|vpiFullName:work@tb_UART.tx
46004600
|vpiActual:
4601-
\_logic_net: (work@tb_UART.uart_inst.tx), line:6:16, endln:6:18
4601+
\_logic_net: (work@tb_UART.tx), line:7:10, endln:7:12
46024602
|vpiLowConn:
46034603
\_ref_obj: (work@tb_UART.uart_inst.tx), line:14:10, endln:14:12
46044604
|vpiParent:
@@ -4629,7 +4629,7 @@ design: (work@tb_UART)
46294629
|vpiName:data
46304630
|vpiFullName:work@tb_UART.data
46314631
|vpiActual:
4632-
\_logic_net: (work@tb_UART.uart_inst.data), line:7:17, endln:7:21
4632+
\_logic_net: (work@tb_UART.data), line:6:15, endln:6:19
46334633
|vpiLowConn:
46344634
\_ref_obj: (work@tb_UART.uart_inst.data), line:15:10, endln:15:14
46354635
|vpiParent:
@@ -4660,7 +4660,7 @@ design: (work@tb_UART)
46604660
|vpiName:send
46614661
|vpiFullName:work@tb_UART.send
46624662
|vpiActual:
4663-
\_logic_net: (work@tb_UART.uart_inst.send), line:8:11, endln:8:15
4663+
\_logic_net: (work@tb_UART.send), line:4:21, endln:4:25
46644664
|vpiLowConn:
46654665
\_ref_obj: (work@tb_UART.uart_inst.send), line:16:10, endln:16:14
46664666
|vpiParent:
@@ -4691,7 +4691,7 @@ design: (work@tb_UART)
46914691
|vpiName:done
46924692
|vpiFullName:work@tb_UART.done
46934693
|vpiActual:
4694-
\_logic_net: (work@tb_UART.uart_inst.done), line:9:16, endln:9:20
4694+
\_logic_net: (work@tb_UART.done), line:7:14, endln:7:18
46954695
|vpiLowConn:
46964696
\_ref_obj: (work@tb_UART.uart_inst.done), line:17:10, endln:17:14
46974697
|vpiParent:
@@ -5863,7 +5863,7 @@ design: (work@tb_UART)
58635863
|vpiName:clk
58645864
|vpiFullName:work@tb_UART.clk
58655865
|vpiActual:
5866-
\_logic_net: (work@tb_UART.uart_inst.uut.clk), line:71:11, endln:71:14
5866+
\_logic_net: (work@tb_UART.uart_inst.clk), line:3:11, endln:3:14
58675867
|vpiLowConn:
58685868
\_ref_obj: (work@tb_UART.uut.clk), line:100:32, endln:100:35
58695869
|vpiParent:
@@ -5894,7 +5894,7 @@ design: (work@tb_UART)
58945894
|vpiName:rst_n
58955895
|vpiFullName:work@tb_UART.rst_n
58965896
|vpiActual:
5897-
\_logic_net: (work@tb_UART.uart_inst.uut.rst_n), line:72:11, endln:72:16
5897+
\_logic_net: (work@tb_UART.uart_inst.rst_n), line:4:11, endln:4:16
58985898
|vpiLowConn:
58995899
\_ref_obj: (work@tb_UART.uut.rst_n), line:100:42, endln:100:47
59005900
|vpiParent:
@@ -5925,7 +5925,7 @@ design: (work@tb_UART)
59255925
|vpiName:send
59265926
|vpiFullName:work@tb_UART.send
59275927
|vpiActual:
5928-
\_logic_net: (work@tb_UART.uart_inst.uut.send), line:73:11, endln:73:15
5928+
\_logic_net: (work@tb_UART.uart_inst.send), line:8:11, endln:8:15
59295929
|vpiLowConn:
59305930
\_ref_obj: (work@tb_UART.uut.send), line:100:56, endln:100:60
59315931
|vpiParent:
@@ -5956,7 +5956,7 @@ design: (work@tb_UART)
59565956
|vpiName:done
59575957
|vpiFullName:work@tb_UART.done
59585958
|vpiActual:
5959-
\_logic_net: (work@tb_UART.uart_inst.uut.done), line:74:11, endln:74:15
5959+
\_logic_net: (work@tb_UART.uart_inst.done), line:9:16, endln:9:20
59605960
|vpiLowConn:
59615961
\_ref_obj: (work@tb_UART.uut.done), line:100:68, endln:100:72
59625962
|vpiParent:

‎tests/Attributes/Attributes.log‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2646,7 +2646,7 @@ design: (work@foo)
26462646
|vpiName:clk
26472647
|vpiFullName:work@foo.clk
26482648
|vpiActual:
2649-
\_logic_net: (work@foo.bar_instance.clk), line:1:12, endln:1:15
2649+
\_logic_net: (work@foo.clk), line:13:12, endln:13:15
26502650
|vpiLowConn:
26512651
\_ref_obj: (work@foo.bar_instance.clk), line:19:52, endln:19:55
26522652
|vpiParent:
@@ -2683,7 +2683,7 @@ design: (work@foo)
26832683
|vpiName:rst
26842684
|vpiFullName:work@foo.rst
26852685
|vpiActual:
2686-
\_logic_net: (work@foo.bar_instance.rst), line:1:17, endln:1:20
2686+
\_logic_net: (work@foo.rst), line:13:17, endln:13:20
26872687
|vpiLowConn:
26882688
\_ref_obj: (work@foo.bar_instance.rst), line:19:57, endln:19:60
26892689
|vpiParent:
@@ -2714,7 +2714,7 @@ design: (work@foo)
27142714
|vpiName:inp
27152715
|vpiFullName:work@foo.inp
27162716
|vpiActual:
2717-
\_logic_net: (work@foo.bar_instance.inp), line:1:22, endln:1:25
2717+
\_logic_net: (work@foo.inp), line:13:22, endln:13:25
27182718
|vpiLowConn:
27192719
\_ref_obj: (work@foo.bar_instance.inp), line:19:95, endln:19:98
27202720
|vpiParent:
@@ -2751,7 +2751,7 @@ design: (work@foo)
27512751
|vpiName:out
27522752
|vpiFullName:work@foo.out
27532753
|vpiActual:
2754-
\_logic_net: (work@foo.bar_instance.out), line:1:27, endln:1:30
2754+
\_logic_net: (work@foo.out), line:13:27, endln:13:30
27552755
|vpiLowConn:
27562756
\_ref_obj: (work@foo.bar_instance.out), line:19:100, endln:19:103
27572757
|vpiParent:

‎tests/Attributes2/Attributes2.log‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1062,7 +1062,7 @@ design: (work@foo)
10621062
|vpiName:clk
10631063
|vpiFullName:work@foo.clk
10641064
|vpiActual:
1065-
\_logic_net: (work@foo.bar_instance_1.clk), line:2:12, endln:2:15
1065+
\_logic_net: (work@foo.clk), line:8:12, endln:8:15
10661066
|vpiLowConn:
10671067
\_ref_obj: (work@foo.bar_instance_1.clk), line:11:45, endln:11:48
10681068
|vpiParent:

‎tests/BindStmt/BindStmt.log‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1495,7 +1495,7 @@ design: (work@testbench)
14951495
|vpiName:a
14961496
|vpiFullName:work@testbench.a
14971497
|vpiActual:
1498-
\_logic_net: (work@testbench.u1.lce_tracer2.a), line:13:75, endln:13:76
1498+
\_logic_net: (work@testbench.u1.a), line:1:55, endln:1:56
14991499
|vpiLowConn:
15001500
\_ref_obj: (work@testbench.lce_tracer2.a), line:13:75, endln:13:76
15011501
|vpiParent:
@@ -1526,7 +1526,7 @@ design: (work@testbench)
15261526
|vpiName:b
15271527
|vpiFullName:work@testbench.b
15281528
|vpiActual:
1529-
\_logic_net: (work@testbench.u1.lce_tracer2.b), line:13:91, endln:13:92
1529+
\_logic_net: (work@testbench.u1.b), line:1:71, endln:1:72
15301530
|vpiLowConn:
15311531
\_ref_obj: (work@testbench.lce_tracer2.b), line:13:91, endln:13:92
15321532
|vpiParent:
@@ -1557,7 +1557,7 @@ design: (work@testbench)
15571557
|vpiName:clk
15581558
|vpiFullName:work@testbench.clk
15591559
|vpiActual:
1560-
\_logic_net: (work@testbench.u1.lce_tracer2.clk), line:13:106, endln:13:109
1560+
\_logic_net: (work@testbench.clk), line:25:31, endln:25:34
15611561
|vpiLowConn:
15621562
\_ref_obj: (work@testbench.lce_tracer2.clk), line:13:106, endln:13:109
15631563
|vpiParent:
@@ -2035,7 +2035,7 @@ design: (work@testbench)
20352035
|vpiName:a
20362036
|vpiFullName:work@testbench.tt.a
20372037
|vpiActual:
2038-
\_logic_net: (work@testbench.tt.u1.lce_tracer2.a), line:13:75, endln:13:76
2038+
\_logic_net: (work@testbench.tt.u1.a), line:1:55, endln:1:56
20392039
|vpiLowConn:
20402040
\_ref_obj: (work@testbench.tt.lce_tracer2.a), line:13:75, endln:13:76
20412041
|vpiParent:
@@ -2066,7 +2066,7 @@ design: (work@testbench)
20662066
|vpiName:b
20672067
|vpiFullName:work@testbench.tt.b
20682068
|vpiActual:
2069-
\_logic_net: (work@testbench.tt.u1.lce_tracer2.b), line:13:91, endln:13:92
2069+
\_logic_net: (work@testbench.tt.u1.b), line:1:71, endln:1:72
20702070
|vpiLowConn:
20712071
\_ref_obj: (work@testbench.tt.lce_tracer2.b), line:13:91, endln:13:92
20722072
|vpiParent:
@@ -2097,7 +2097,7 @@ design: (work@testbench)
20972097
|vpiName:clk
20982098
|vpiFullName:work@testbench.tt.clk
20992099
|vpiActual:
2100-
\_logic_net: (work@testbench.tt.u1.lce_tracer2.clk), line:13:106, endln:13:109
2100+
\_logic_net: (work@testbench.tt.clk)
21012101
|vpiLowConn:
21022102
\_ref_obj: (work@testbench.tt.lce_tracer2.clk), line:13:106, endln:13:109
21032103
|vpiParent:

‎tests/BindStmt2/BindStmt2.log‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2493,7 +2493,7 @@ design: (work@rv_dm)
24932493
|vpiName:clk_i
24942494
|vpiFullName:work@rv_dm.clk_i
24952495
|vpiActual:
2496-
\_bit_var: (work@rv_dm.u_dmidpi.clk_i), line:40:21, endln:40:26
2496+
\_logic_net: (work@rv_dm.clk_i), line:5:30, endln:5:35
24972497
|vpiLowConn:
24982498
\_ref_obj: (work@rv_dm.u_dmidpi.clk_i), line:58:6, endln:58:11
24992499
|vpiParent:
@@ -2524,7 +2524,7 @@ design: (work@rv_dm)
25242524
|vpiName:rst_ni
25252525
|vpiFullName:work@rv_dm.rst_ni
25262526
|vpiActual:
2527-
\_bit_var: (work@rv_dm.u_dmidpi.rst_ni), line:41:21, endln:41:27
2527+
\_logic_net: (work@rv_dm.rst_ni), line:6:30, endln:6:36
25282528
|vpiLowConn:
25292529
\_ref_obj: (work@rv_dm.u_dmidpi.rst_ni), line:59:6, endln:59:12
25302530
|vpiParent:
@@ -2555,7 +2555,7 @@ design: (work@rv_dm)
25552555
|vpiName:dmi_req_valid
25562556
|vpiFullName:work@rv_dm.dmi_req_valid
25572557
|vpiActual:
2558-
\_bit_var: (work@rv_dm.u_dmidpi.dmi_req_valid), line:43:21, endln:43:34
2558+
\_logic_var: (work@rv_dm.dmi_req_valid), line:30:9, endln:30:22
25592559
|vpiLowConn:
25602560
\_ref_obj: (work@rv_dm.u_dmidpi.dmi_req_valid), line:60:6, endln:60:19
25612561
|vpiParent:
@@ -2586,7 +2586,7 @@ design: (work@rv_dm)
25862586
|vpiName:dmi_req_ready
25872587
|vpiFullName:work@rv_dm.dmi_req_ready
25882588
|vpiActual:
2589-
\_bit_var: (work@rv_dm.u_dmidpi.dmi_req_ready), line:44:21, endln:44:34
2589+
\_logic_var: (work@rv_dm.dmi_req_ready), line:30:24, endln:30:37
25902590
|vpiLowConn:
25912591
\_ref_obj: (work@rv_dm.u_dmidpi.dmi_req_ready), line:61:6, endln:61:19
25922592
|vpiParent:
@@ -2746,7 +2746,7 @@ design: (work@rv_dm)
27462746
|vpiName:dmi_rsp_valid
27472747
|vpiFullName:work@rv_dm.dmi_rsp_valid
27482748
|vpiActual:
2749-
\_bit_var: (work@rv_dm.u_dmidpi.dmi_rsp_valid), line:48:21, endln:48:34
2749+
\_logic_var: (work@rv_dm.dmi_rsp_valid), line:31:9, endln:31:22
27502750
|vpiLowConn:
27512751
\_ref_obj: (work@rv_dm.u_dmidpi.dmi_rsp_valid), line:65:6, endln:65:19
27522752
|vpiParent:
@@ -2777,7 +2777,7 @@ design: (work@rv_dm)
27772777
|vpiName:dmi_rsp_ready
27782778
|vpiFullName:work@rv_dm.dmi_rsp_ready
27792779
|vpiActual:
2780-
\_bit_var: (work@rv_dm.u_dmidpi.dmi_rsp_ready), line:49:21, endln:49:34
2780+
\_logic_var: (work@rv_dm.dmi_rsp_ready), line:31:24, endln:31:37
27812781
|vpiLowConn:
27822782
\_ref_obj: (work@rv_dm.u_dmidpi.dmi_rsp_ready), line:66:6, endln:66:19
27832783
|vpiParent:
@@ -2894,7 +2894,7 @@ design: (work@rv_dm)
28942894
|vpiName:dmi_rst_n
28952895
|vpiFullName:work@rv_dm.dmi_rst_n
28962896
|vpiActual:
2897-
\_bit_var: (work@rv_dm.u_dmidpi.dmi_rst_n), line:52:21, endln:52:30
2897+
\_logic_var: (work@rv_dm.dmi_rst_n), line:32:9, endln:32:18
28982898
|vpiLowConn:
28992899
\_ref_obj: (work@rv_dm.u_dmidpi.dmi_rst_n), line:69:6, endln:69:15
29002900
|vpiParent:

‎tests/BindingPort/BindingPort.log‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -236,7 +236,7 @@ design: (work@UART)
236236
|vpiName:clk
237237
|vpiFullName:work@UART.clk
238238
|vpiActual:
239-
\_logic_net: (work@UART.uut.clk), line:14:11, endln:14:14
239+
\_logic_net: (work@UART.clk), line:5:11, endln:5:14
240240
|vpiLowConn:
241241
\_ref_obj: (work@UART.uut.clk), line:22:38, endln:22:43
242242
|vpiParent:

‎tests/ComplexParamOverload2/ComplexParamOverload2.log‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1206,7 +1206,7 @@ design: (work@top)
12061206
|vpiName:o
12071207
|vpiFullName:work@top.u_top.u_prim_pad_attr.o
12081208
|vpiActual:
1209-
\_int_var: (work@top.u_top.u_prim_pad_attr.u_submodule.o), line:24:34, endln:24:35
1209+
\_logic_net: (work@top.u_top.u_prim_pad_attr.o), line:41:10, endln:41:11
12101210
|vpiLowConn:
12111211
\_ref_obj: (work@top.u_top.u_prim_pad_attr.u_submodule.o), line:41:8, endln:41:9
12121212
|vpiParent:
@@ -1300,7 +1300,7 @@ design: (work@top)
13001300
|vpiName:o
13011301
|vpiFullName:work@top.u_top.u_prim_pad_attr.u_submodule.o
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|vpiActual:
1303-
\_int_var: (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic.o), line:19:41, endln:19:42
1303+
\_int_var: (work@top.u_top.u_prim_pad_attr.u_submodule.o), line:24:34, endln:24:35
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|vpiLowConn:
13051305
\_ref_obj: (work@top.u_top.u_prim_pad_attr.u_submodule.u_impl_generic.o), line:30:8, endln:30:9
13061306
|vpiParent:

‎tests/DefaultNetType/DefaultNetType.log‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1328,7 +1328,7 @@ design: (work@ok)
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|vpiName:b
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|vpiFullName:work@bad2.b
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|vpiActual:
1331-
\_logic_net: (work@bad2.m1.b), line:11:17, endln:11:18
1331+
\_logic_net: (work@bad2.b), line:47:7, endln:47:8
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|vpiLowConn:
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\_ref_obj: (work@bad2.m1.b), line:47:7, endln:47:8
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|vpiParent:

‎tests/Delay2Param/Delay2Param.log‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1146,7 +1146,7 @@ design: (work@iNToRecFN)
11461146
|vpiName:signedIn
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|vpiFullName:work@iNToRecFN.signedIn
11481148
|vpiActual:
1149-
\_logic_net: (work@iNToRecFN.iNToRawFN.signedIn), line:1:44, endln:1:52
1149+
\_logic_net: (work@iNToRecFN.signedIn), line:24:33, endln:24:41
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|vpiLowConn:
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\_ref_obj: (work@iNToRecFN.iNToRawFN.signedIn), line:1:44, endln:1:52
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|vpiParent:
@@ -1170,7 +1170,7 @@ design: (work@iNToRecFN)
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|vpiName:sExp
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|vpiFullName:work@iNToRecFN.sExp
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|vpiActual:
1173-
\_logic_net: (work@iNToRecFN.iNToRawFN.sExp), line:1:54, endln:1:58
1173+
\_logic_net: (work@iNToRecFN.sExp), line:24:43, endln:24:47
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|vpiLowConn:
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\_ref_obj: (work@iNToRecFN.iNToRawFN.sExp), line:1:54, endln:1:58
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|vpiParent:
@@ -1359,7 +1359,7 @@ design: (work@iNToRecFN)
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|vpiName:signedIn
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|vpiFullName:work@iNToRecFN.signedIn
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|vpiActual:
1362-
\_logic_net: (work@iNToRecFN.iNToRawFN3.signedIn), line:6:70, endln:6:78
1362+
\_logic_net: (work@iNToRecFN.signedIn), line:24:33, endln:24:41
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|vpiLowConn:
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\_ref_obj: (work@iNToRecFN.iNToRawFN3.signedIn), line:6:70, endln:6:78
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|vpiParent:
@@ -1383,7 +1383,7 @@ design: (work@iNToRecFN)
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|vpiName:sExp
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|vpiFullName:work@iNToRecFN.sExp
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|vpiActual:
1386-
\_logic_net: (work@iNToRecFN.iNToRawFN3.sExp), line:6:80, endln:6:84
1386+
\_logic_net: (work@iNToRecFN.sExp), line:24:43, endln:24:47
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|vpiLowConn:
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\_ref_obj: (work@iNToRecFN.iNToRawFN3.sExp), line:6:80, endln:6:84
13891389
|vpiParent:

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