sysverilog-airhdl-demo

This project is learning space for System Verilog with AIRHDL and SPI to AXI4-Lite.

Still a work in progress.

TODO: In particular the TCL script is not yet working right, I need to confirm the format of the data of the bus matches the AIRHDL spec.

References:

• https://www.xilinx.com/support/download.html
• https://zyedidia.github.io/notes/sv_guide.pdf
• https://airhdl.com
• https://github.com/airhdl/spi-to-axi-bridge