Supports 4-soc running on FPGA #12
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Since FPGA on-board memory has one cycle latency. So InstructionFetch stage is necessary to split to IF1 and IF2, then instruction address ports splits to two different ports: instruction_req for IF1 instruction_address for IF2. Then from InstructionFetch module to Top module, all connecting ports also need to modify correspondingly.
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Since FPGA on-board memory has one cycle latency. So InstructionFetch stage is necessary to split to IF1 and IF2, then instruction address ports splits to two different ports:
instruction_req for IF1
instruction_address for IF2.
Then from InstructionFetch module to Top module, all connecting ports also need to modify correspondingly.
There are two options for implementation:
Like this PR, separates to /fpga and /verilator for modified files in /riscv/core and /board.
branch logic for fpga and verilator directly in original code. Preventing separating source code in two different places.