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@jgw0915 jgw0915 commented Jan 12, 2026

Solving issue mentioned by @eastWillow

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jserv commented Jan 20, 2026

I defer to @eastWillow for confirmation.

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@jgw0915 jgw0915 force-pushed the Control-Hazard-Logic branch 2 times, most recently from 7e14aa8 to 878a0ce Compare January 20, 2026 17:25
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jgw0915 commented Jan 20, 2026

Hi @eastWillow, I have made an update on this PR. Please check it out.

@jgw0915 jgw0915 requested a review from jserv January 20, 2026 17:32
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@jgw0915 jgw0915 force-pushed the Control-Hazard-Logic branch 2 times, most recently from 9d648f6 to 3c78cba Compare January 21, 2026 06:16
@jgw0915 jgw0915 changed the title Feat/ Implementation of fall stall prevention in five-stage stall and forwarding CPU Feat/ Fall stall prevention in pipeline CPUs Jan 21, 2026
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jgw0915 commented Jan 21, 2026

Hi @eastWillow, I have made an update on this PR. Please check it out.

@jgw0915 jgw0915 requested a review from jserv January 21, 2026 06:17
@jgw0915 jgw0915 force-pushed the Control-Hazard-Logic branch from 3c78cba to 429ca3d Compare January 21, 2026 07:37
@jgw0915 jgw0915 changed the title Feat/ Fall stall prevention in pipeline CPUs Feature fall stall prevention in pipeline CPUs Jan 21, 2026
val memory_read_enable_ex = Input(Bool()) // id2ex.io.output_memory_read_enable
val rd_ex = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) // id2ex.io.output_regs_write_address
val uses_rs1_id = Input(Bool()) // true only if current ID instruction really reads rs1
val uses_rs2_id = Input(Bool())
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This should match the comment in fivestage_stall/Control.scala.

Suggested change
val uses_rs2_id = Input(Bool())
val uses_rs2_id = Input(Bool()) // true only if current ID instruction really reads rs2

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I noticed that 3-pipeline/csrc/hazard_extended.S was updated in PR #8, the corresponding hazard_extended.asmbin was not.

sbt "project pipeline" test doesn't recompile assembly source files automatically, could you please also update the .asmbin file in this PR? This will ensure the binary stays in sync with the source and prevent test discrepancies."

Add uses_rs1_id/uses_rs2_id from decode and feed them into stall/forward CPU's control unit so hazard checks know which operands are real.

Without gating, stall logic can misread a lw’s immediate bits as an rs2 match, causing false load-use stalls/flushes. We now guard comparisons with uses_rs1_id/uses_rs2_id to avoid that.

Unused operand read addresses are driven to x0 to keep dependency matching consistent and prevent accidental collisions.
@jgw0915 jgw0915 force-pushed the Control-Hazard-Logic branch from ed47301 to 986db74 Compare January 29, 2026 08:21
@jgw0915 jgw0915 requested a review from eastWillow January 29, 2026 08:22
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I locally rebased my solution with this Pull Request.
Running sbt "project pipeline" test passed successfully.
[success] Total time: 47 s, completed Jan 31, 2026 6:25:19 AM

Thanks for the great work! I don't have any further suggestions.

Thanks @jgw0915 for contributing!

@jserv jserv merged commit 6664a34 into sysprog21:main Jan 31, 2026
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jserv commented Jan 31, 2026

Thank @jgw0915 for contributing!

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3 participants