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Feature fall stall prevention in pipeline CPUs #13
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I defer to @eastWillow for confirmation. |
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Hi @eastWillow, I have made an update on this PR. Please check it out. |
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Enforce the rules specified in https://chris.beams.io/git-commit carefully.
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Hi @eastWillow, I have made an update on this PR. Please check it out. |
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| val memory_read_enable_ex = Input(Bool()) // id2ex.io.output_memory_read_enable | ||
| val rd_ex = Input(UInt(Parameters.PhysicalRegisterAddrWidth)) // id2ex.io.output_regs_write_address | ||
| val uses_rs1_id = Input(Bool()) // true only if current ID instruction really reads rs1 | ||
| val uses_rs2_id = Input(Bool()) |
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This should match the comment in fivestage_stall/Control.scala.
| val uses_rs2_id = Input(Bool()) | |
| val uses_rs2_id = Input(Bool()) // true only if current ID instruction really reads rs2 |
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I noticed that 3-pipeline/csrc/hazard_extended.S was updated in PR #8, the corresponding hazard_extended.asmbin was not.
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Add uses_rs1_id/uses_rs2_id from decode and feed them into stall/forward CPU's control unit so hazard checks know which operands are real. Without gating, stall logic can misread a lw’s immediate bits as an rs2 match, causing false load-use stalls/flushes. We now guard comparisons with uses_rs1_id/uses_rs2_id to avoid that. Unused operand read addresses are driven to x0 to keep dependency matching consistent and prevent accidental collisions.
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I locally rebased my solution with this Pull Request.
Running sbt "project pipeline" test passed successfully.
[success] Total time: 47 s, completed Jan 31, 2026 6:25:19 AM
Thanks for the great work! I don't have any further suggestions.
Thanks @jgw0915 for contributing!
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Thank @jgw0915 for contributing! |
Solving issue mentioned by @eastWillow